A continuing goal of semiconductor device fabrication is to increase the number of devices associated with a given area of semiconductor real estate to thereby achieve an increased level of integration. One facet of such goal is to scale new generations of devices to be smaller than preceding generations.
Many modern electronic systems utilize nonvolatile memory (flash memory). It is desired to increase the level of integration of flash memory. However, a problem occurs in scaling flash memory cells in trying to achieve desired coupling between control and floating gates while avoiding undesired interference between adjacent floating gates. A prior art method which has been developed to address such problem is discussed with reference to FIGS. 1-4.
FIG. 1 shows a semiconductor construction 10 comprising a base 12 having a series of isolation regions 14 extending therein, and comprising floating gates 16 spaced from one another by the isolation regions.
Base 12 may comprise, consist essentially of, or consist of, for example, monocrystalline silicon lightly-doped with background p-type dopant, and may be referred to as a semiconductor substrate. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Isolation regions 14 comprise insulative material 18 extending into trenches within base 12. Insulative material 18 may, for example, comprise, consist essentially of, or consist of silicon dioxide.
Active regions 20 correspond to pillars of base 12 between the isolation regions. The floating gates 16 are formed over the active regions, and separated from the active regions by gate dielectric 22. The gate dielectric may comprise, consist essentially of, or consist of silicon dioxide, and may be referred to as tunnel oxide.
The floating gates 16 comprise two conductive portions 24 and 26, with the portion 24 being wider than the portion 26 in the shown cross-sectional view. Accordingly, portions 24 and 26 together form an inverted “T” shape. The narrow portions 26 of the adjacent floating gates are spaced from one another by a gap 27. It is noted that the inverted “T” shape of the floating gates allows gap 27 to the wider than the gap between the adjacent active regions 20.
The portions 24 and 26 may comprise the same composition as one another, and may, for example, both consist essentially of, or consist of conductively-doped polycrystalline silicon. It is noted that if portions 24 and 26 comprise the same composition as one another, the portions merge to form a single structure. However, the portions are shown separate from one another in FIG. 1 to aid in the description of the structure.
A pair of electrically insulative spacers 28 are adjacent the narrow portions 26 of the floating gates to fill space between the narrow portions and the isolation regions 14.
FIG. 2 shows the floating gates of FIG. 1 incorporated into flash cells 30 and 32. Specifically, dielectric material 34 is provided over the floating gates and within the gap 27 between the floating gates; and control gate material 36 is provided over the dielectric material and also within the gap between the floating gates. The dielectric material 34 may, for example, comprise, consist essentially of, or consist of a stack of silicon dioxide/silicon nitride/silicon dioxide (in other words, a so-called ONO stack). The control gate material 36 may comprise any suitable electrically conductive composition or combination of compositions, including, for example, metals, metal compositions, and/or conductively-doped semiconductor material
In some applications, the distance between the adjacent active regions 20 may be 35 nanometers, while the distance between the narrow portions 26 of the floating gates is about 50 nanometers. The dielectric material 34 and control gate material 36 may fit within a space of 50 nanometers, but it would be difficult to fit them within a space of 35 nanometers.
FIGS. 3 and 4 illustrate a method of forming the construction of FIG. 1. FIG. 3 shows construction 10 at a processing stage in which spacers 28 are formed over the first portion 24 of the floating gates to leave openings over the first portion 24. FIG. 4 shows a subsequent processing stage in which polycrystalline silicon 38 is deposited to fill the openings. The construction may then be subjected to planarization followed by an etchback of materials 18 and 28 to form the structure of FIG. 1. Portion 24 and material 38 are shown to not be conductively-doped at the processing stages of FIGS. 3 and 4; implying that the conductive doping will occur between the processing stage of FIG. 4 and the stage shown in FIG. 1. It is to be understood, however, the conductive doping may occur at numerous processing stages. For instance, portions 24 may be conductively-doped prior to the processing stage of FIG. 3; and material 38 may be in situ doped during the deposition of material 38.
It is desired to develop improved methods for forming semiconductor devices, and to develop improved semiconductor structures.